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    Using Pynq Z2 FPGA to connect a camera (OV7670 - CMOS Sensor), and then display the video on a monitor through HDMI output. The Project is built using VHDL language and IP blocks. The purpose of this it's to build also nurual network to recognize a face/person so the camera can follow the object using servo motor.

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    Hello, I'm hiring a dev who's very hot with FGPA. Need him to create cryptocurrency miner/blockchain. Specificly Xilinx Alveo U200 & U250 Cards. I can pay a lot. Contact me I'm very active. #FPGA - #XILINX #ALVEO #ALVEOu200 #ALVEOu250 #XRT #MINING #CRYPTO #DEVELOPPER #FREELANCER #FREELANCE

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    I need to implement a complete FPGA system using Verilog in Vivado Design Suite. Professional FPGA experts are required. Please find the details of the project in the attachment.

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    FEC RS(198, 194) 3 days left

    Verilog FPGA Code implementation of FEC RS(198, 194) decoder.

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    ...have an internal project for 5G RAN FPGA design for DFE products: Skills: Job Description- Senior MTS RTL design 5G Product( 2 positions) · Candidate must have at least Bachelors or Masters EE - FPGA design experience (RTL Coding, comms, DFE(DPD, DUC, DDC, FFT, FIR, CFR) · Candidate must have verifiable experience for a minimum 6 years as a Verilog/System Verilog/ VHDL/RTL programmer with extensive Verification test bench development experience · Preferred prior project experience in 5G ORAN - RU/DU. DSP knowledge Matlab modeling is preferred. · eCPRI experience preferred . Special consideration will be given to those who have experience as 100G Ethernet or 10G Ethernet , IEEE 1588 · Knowledge of Queuing theory · Tools &nd...

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    The project consists in implementing a buffer delay on a 100G traffic done in an Xilinx Alveo FPGA

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    I need to design a Hilbert transform and test it in Matlab before implementing it on FPGA. I have never created a Hilbert transform with Matlab without the hilbert() function, and the function does not return coefficients. I can't find the documentation on how to do it. I need someone to help with it. The Matlab code must also use the filter on sample data and return complex values after the transform. You should provide the Matlab code used to create the filter and get the coefficients. I will pay $70 USD for the task.

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    Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    The goal of the project is to design both hardware (PCB) and software for a low cost,small sized, digital video transmit...The interested designer can choose any processor or RF IC as per their wish but QFN/QFPN based IC will be preferable as they are easier to the image sensors/camera module should also be integrated into the AIO flight Controller can be based on Allwinner T113-S3 microprocessor or an FPGA but should contain Gyroscope, accelerometer, pressure/ project report will be sent to the intrested designers on request. An AI SoM board based on Rockchip/FPGA will also has to be developed under the design. The prototyping task will be undertaken by ourselves only the design of the video transmitter and the flight Controller needs to be done.

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    Hello, I need a Lattice FPGA specialist to review my simple LCMX02 Lattice PLD design. I can not make it work, and some help is needed to understand why the PLD does not respond to the JTAG file. This is a very specific project, specifically for Lattice FPGA. I designed with other types of FPGA, and got stuck when I switched to Lattice family of parts. Thank you!

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    code for SPI master to send data to a GPU. project setup for the customer's terasic FPGA board. assignment. demonstration of contents via zoom meeting. I will try to complete the project before the specified end date.

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    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    Creating 2-chain Arbiter PUF on specific FPGA with 64-stages MUX for each chain. The output response PUF will be sent to external device, i.e. Arduino (microcontroller). On the other words, the output response PUF will be processed further on Arduino/microcontroller device

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    It is required to generate arbitrary signals in FPGA for Real Time Controls using Servo Proportional Valve with Control signals of ( +/- 10 VDC ). The various types of other signal generation in FPGA besides Arbitrary signal can be Square, Sine, Triangular. Generation of white noise signal for Real time control is also required.

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    Need help with code and set up for SPI protocol to send data from an FPGA to a GPU, explain code/software procedure and wiring. can forward technical specs for both devices to be used

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    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project.

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    A complete color sorter Machine Firmware needs to be converted into Intel Quartus Project, The project contains IP Cores as well as softcore processor and the verilog coding part, All these to be integrated as a single bit file and to be implemented it on a Cyclone V FPGA Board.

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    Hi. Attached a few spike from scope capture. Need at least 8 channels simultaniously. 1. how to get detect these with a precision of 1mV? 2. how to get the value in stm32? (worked with these a lot) (or do we need an fpga) Freq is 200hz at first. Looking to get to 1 khz in the near future. Duration of the spike is only 5 to 12 microseconds. What is the best way to do this precisely ? heard tons of ideas (peak-detect circuit, 20 msps adc, etc ) , but need real proven experience. !!! please apply only if done this succefully. In the opening bid propose direclty your solution. Biggest bids will be disqualified. Stop bidding the top of freelancers brackets. No B*****S approach. Will be paid only if it WORKS! Need STM32 code, parts id, and pcb design.

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    LabView- Code for FPGA to read temperatures from MLX90614 Sensor using I2C Protocol and Compact-RIO Hardware.

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    The project requires an Embedded Programmer having experience in Driver Programming for FPGA cards, PCIe Interface and YOCTO as well as upbringing the Linux OS. Please DO NOT APPLY, if you DO NOT HAVE THE REQUIRED EXPERIENCE.

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    I need a survey paper based on 3 articles at your choose from with publication date more recent then 2010. The articles has to be based on one topic from the following. Theme variants: A. Digital signal processor architectures (e.g .: DSP, ...recent then 2010. The articles has to be based on one topic from the following. Theme variants: A. Digital signal processor architectures (e.g .: DSP, VLIW, etc.) B. Micro-architectures optimized for digital signal processing (e.g., multi-port memory, SIMD register banks, multi-core, multi-threading, etc.) C. Accelerators for digital signal processing (rapid deployments / energy efficient with FPGA, GPU, etc.) The paper must be written in latex format. 4 pages, 3-4 figures (explained) and also some references from other articles.

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    Implement the circuit design in the FPGA, and read input /write output to the file. Including timing analysis, power consumption and pin planner etc... Using Quartus prime

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    I need to do simple FPGA project on Boolean Board (Real Digital). For example Tic Tac Toe game. software should be Vivado and programming should be done in Verilog.

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    Program on vivado (verilog), morse code. Binary for "BASYS 3" fpga, simulation, files...etc More details via chat

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    ...sent) and get quotes from them. I will provide an email you can use to email each vendor. I have also provided a link to the item. They can’t be any random emails. I need screenshots of the company’s website and the contact information for each company. Item: FPGA STRATIX 10 2912FBGA (1SX250HH2F55E2VG) Part Link: Hello, my name is Edwin Mendez. I am writing this email on behalf of my company. We are looking for a particular part. The part that we are searching for is the FPGA STRATIX 10 2912FBGA (1SX250HH2F55E2VG). We need three of these parts ASAP. It would be great if you can provide us with this particular part. We are ready for any deal regarding the price structure. We can also schedule a meeting for any further discussions.

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    I need to implement an Ed25519 Algorithm in Verilog for FPGA implementation that can properly simulate on Xilinx Vivado Design Suite. The complete algorithm code is already available in C language and I want to convert it into Verilog. Link:

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    I have rich experience with FPGA I developed FPGA based IDS(Intrusion Detection System) I am strong at C, C++, Verilog and son on

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    using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C , C++

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    We hire freelancers who have 1 to 3 hours of free time per day and need a better iPhone 7 or above that can perform and complete testing tasks well. Test system design. Areas of expertise include embedded system/FPGA development, hardware prototype stability and testing. We make the world a better place through innovation and collaboration. From the bottom of the ocean to outer space, you can contribute to the important work of a company whose values are made up of diversity, fairness and inclusion. We are committed to creating a warm, respectful and inclusive environment for all of our teammates and providing them with good career development opportunities. Find the future with us.

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    I am looking for embedded developer to help me on preparing linux image for FPGA and SOC chip . Have samples and you need to follow and prepare the image

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    I am looking for an electrical engineer who can work on FPGA TEST Board design. The project is to design FPGA TEST Board for XC7VX690T-2FFG1157I chip. We need power supply connectors as Banana jack and JTAG, UART, and SPI flash, and other decoupling capacitors and resistors. We just need simple workable Sch and PCB design wit optimal design. The candidate should have rich experience in FPGA PCB design using Altium.

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    We are looking for electrical and electronics engineers with good experience in following areas: • Embedded C Programming. • VHDL/Verilog, LabVIEW/ Multisim/PSPICE • Network Simulator NS2/NS3 • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. Feel free to place your bid and mention your areas of expertise in your proposal. we highly encourage new freelancers to apply for this post.

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    GPU cryptocurrency mining is not able to keep up with the power of FPGAs and ASIC miners. I would like to purchase FPGAs for cryptocurrency mining (at present it would be for the Kaspa coin, ). I have not selected an FPGA and am happy for recommendations, for this reason, I am looking for a programmer with a proven track record in the cryptocurrency mining area. there is GPU open-source software for this coin

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    Featured Sealed NDA
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    ok before we had a paper to review about floating point adder in fpga i already did but there is the furue work of that paper talking about specific topic for improvment if u could help me with it (far and close path algorithms).

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    using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C , C++

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    1. "idle" state: It is the state when the machine is doing nothing and is idle. In "idle" state, if power button is "on" then the state transition takes place from state "idle" to state "a" and the output is low. If power button is "off ", then the state remains in "idle". 2. "a" state: In state "a", if fill_water is 1(that is if the water gets filled) then the...the water is filled that is if fill_water = 1, then the process gets completed and the state returns back to its idle state and the output is 1. Otherwise it remains in state "c". and in state a it depends on weight for example : 0-2 kilo 3 seconds to fill water 3-5 kilos 5 seconds 6-7 kilos 8 seconds for the weight 3bit for the s...

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    Verilog/VhDL FPGA Asic Electronics Microcontroller

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    Dear sir, this is to document our project for FPGA Game on Intel ARM Processor. All materials are submitted and voice notes as an explanation for the project. Kindly please release to be able to finish the project. This is for 46 hours of work. We can not use international transactions as this takes a lot of time and can be blocked. If you have a counteroffer to reduce the number of hours, please send me. In addition, kindly please send me the SWIFT too. Kindly please check the game working here Kindest regards.

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    I have a Xilinx KV260 board. Would like to develop a small robot project based on Vitis AI or PYNQ libraries. Need some simple documentation for education purposes. Be able to communicate.

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    There are about 10 prompts (design + testbench) that need to be written in Verilog. Message me personally for the prompts. I need it done as soon as possible.

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    Hi, We have a few projects which require very good knowledge of FPGA and Verilog. Please give me your bids stating, 1. Your total relevant experience in FPGA/Verilog. 2. Past Projects history/Experience. 3. How many hours you can spend weekly? Interested and well experienced candidates are most welcomed!

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    The project is to develop an application based on FPGA development board with interfacing Analog Eval. board for processing audio signal. Here is details : H/W will be used : 1- Zynq Zedboard or MPSOC development board. 2- AD7134 dual chip AD Development board. Both boards connected by FMC LPC/HPC connector. S/W - F/W : 1- AD7134 is supported by AD and it has all firmware required to interface to many fpga board, so we can use this ready HDL/DRIVER for interfacing the AD7134 to our fpga board. 2- interfacing to PC through Ethernet with ready library "LIBIIO" or using "Matlab FPGA data capture". We have all hardware development boards on hand, can use it remotely. Any details will be discussed in details.

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    A verilog code by using FPGA to implement an algorithm to merge the bit serial multiplier and bit parallel multiplier which is lead us to get the benefits of the tow methods which is to get the low cost of the bit serial multiplier and the speed or fast performance of bit parallel multiplier. FPGA is basys 3

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    i need ur help in designing an accelerometer sensor and show reading in my fpga kit in vhdl

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    I need a H.264 realtime HD video encoder implemented on FPGA. There are many opensource implementations of H.264 video codec, but there are very few implementations that are running on FPGA. If you can help me, please let me know. I want to accept two approaches. 1) Plain VHDL/Verilog implementation 2) Hardware/Software co-design implementation Whatever approach you choose, the SoC should be able to process realtime video stream.

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    I am trying to build a core (IP) that includes communication between SPI slave and wishbone master. I have written the state machine for both of them. also, I have the codes for both. The issue is that I don"t know how to make both of them communicate in a correct way. I have tried a lot but I was not able to do it. I wish that I can find someone that able to make it work so I can learn from it. I can help you with anything you need also I can provide the codes for you. Please, be aware that I am not willing to pay a lot for this so please make your price reasonable and cheap.

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