I need you to develop some software for me. I would like this software to be developed . You will have to program an FPGA card that I will provide, to work for crypto mining. I will provide the software that works under windows and Linux and you will have to make this software works with the FPGA that will provide to you. Software will have to be
Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position
I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [url removed, login to view] Please respond directly with any questions such as specific mining software and such.
Help me to research and find a suitable FPGA board for my project.
I want to get a simple 3 layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware.
I want to develop a serial interface on my FPGA board, serial communication from host done by Python.
I need help to clear the error in verilog code to make the fpga work. > Modules are already created with 2 feature of audio effects (delay and musical instrument) >Need help to clear the error, edit the code and make it work in fpga > Only 1 bitstream can be generated
...simple: I send 31 bytes from my computer to the FPGA (through UART), the FPGA makes some calculations and then I receive 54 bytes back to my PC (through UART again). The problem is that, I'm not receiving what is expected according to the simulation. Moreover, everytime I send the same bytes to the FPGA, I get back a different answer (which is not possible)
...re-write the FPGA firmware to accommodate a faster ADC chip. We are currently using an 80 MSPS 14 bit ADC (AD9245BCPZ-80), which is the fastest in that specific form factor. Ideally, we would like to go as high as 180 MSPS whilst keeping the board the same size. This would require some re-work of the board and a re-writing of the FPGA code. We do
The task is to implement one direction data flow from FPGA to PC using: 1. Evaluation board Terasic DE0-CV ([url removed, login to view]) and 2. wiz830mj ([url removed, login to view]). The data should be sent to PC by TCP/IP protocol. The correct solution implies Verilog
...细节是用GPIO模仿Jtag烧录两片Xilinx的PROM. (XCF04S, XCF01S). Xilin有比较详细的方案。 见副件。 如果你们承接这类工程， 请你给我一个报价。 我们有硬件平台， 你们需要提供， 1 windows usb 的驱动， 指定等待下载的文件。 Cy7c68013A 的程序，把指定的文件烧录到目标PROM. 启动系统， 读取FPGA内部寄存器，确定烧录成功。
I am looking for someone who is familiar with and have access to the following Electronic systems/subjects: - Op-Amps - Multisim - FPGA/Quartus PRime - Mbed Microcontrollers - Digital Analogue converters (DAC) - using R-2R Ladder If you do not have relevant skills and access please do not apply Thank you
Need a freelancer to port an old Altera(maybe even Xilinx ISE) project into Xilinx Vivado and provide the bitstream to run on a Digilint Zybo Zynq-7010. May be done very quickly since many files are already in a ISE project. Resources: [url removed, login to view] [url removed, login to view]
I need an engineer to design the electronics of our project ([url removed, login to view]). We have a RaspberryPI and need to connect it to Sony sensors (full frame / APS-C) and to Sony EVF. We also use Lattice FPGA to convert the data from the sensor to the PI and from the PI to the Sony EVF.
T...using FPGA. It includes the following: 1.Real-time microphone-speaker system (capture voice from them PmodMIC3 and output at PmodAMP2). 2.Real-time delay in microphone-speaker system. [url removed, login to view] Music Instrument. [url removed, login to view] integration. [url removed, login to view] extra feature (open-ended). Verilog code will be given and it can edit accord...