Questasim jobs
i am looking for an individual who can do perform the project on Quartus in VHDL formate. We are looking for only experts.
Hi I am writing the code for UVM verification environment for the AMBA AHB. I have all the code but facing problems integrating it with errors. It's to be done in vivado or questasim. It's in system verilog language. I need it in 2 days. We could discuss the price based on the difficulty and time you have to give on this.
VHDL , QUARTUS , MODELSIM ALTERA, QUESTASIM, UP DOWN COUNTER , COUNT ZERO COUNTER, CLOCK GENERATOR, RGB CONTROLLER. STATE MACHINE ...
1. Encode key presses on a standard 16-key 2. give a stable 4-bit binary output 3. Have output to indicate when a key is being pressed.
Need someone familiar with verilog programming in Questasim.
The task is to debug and simulate some simple code in VHDL by using QuestaSim.