Verilog projects jobs

Filter

My recent searches
Filter by:
Budget
to
to
to
Type
Skills
Languages
    Job State
    1,443 verilog projects jobs found, pricing in AUD

    more details will be given in the chat only serious expert and my maximum budget for this task is $100

    $78 (Avg Bid)
    $78 Avg Bid
    23 bids

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $1442 (Avg Bid)
    $1442 Avg Bid
    4 bids

    hello, everyone i would like to hire fpga and verilog experts if you have experience on fpga, please bid on my project. thanks.

    $737 (Avg Bid)
    $737 Avg Bid
    20 bids

    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [login to view URL]; a. The source can

    $869 (Avg Bid)
    $869 Avg Bid
    3 bids

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

    $642 (Avg Bid)
    $642 Avg Bid
    10 bids

    I need the matlab developer and verilog developer

    $869 (Avg Bid)
    $869 Avg Bid
    17 bids

    hi, everyone i would like to hire fpga and verilog expert if you have experience on fpga, please bid. thanks.

    $723 (Avg Bid)
    $723 Avg Bid
    24 bids

    verilog code for radix-4 16 point fft

    $21 (Avg Bid)
    $21 Avg Bid
    8 bids

    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

    $22 (Avg Bid)
    $22 Avg Bid
    4 bids

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $16480 (Avg Bid)
    $16480 Avg Bid
    2 bids

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $14439 (Avg Bid)
    $14439 Avg Bid
    1 bids

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $1243 - $1253
    $1243 - $1253
    0 bids

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $1226 - $1227
    $1226 - $1227
    0 bids

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $1229 - $1229
    $1229 - $1229
    0 bids

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $1246 (Avg Bid)
    $1246 Avg Bid
    3 bids

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    $1023 - $1227
    $1023 - $1227
    0 bids

    hi all how are you? this is a verilog question whats output base on testbench? the codes are in txt file

    $72 (Avg Bid)
    $72 Avg Bid
    1 bids

    Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.

    $217 (Avg Bid)
    $217 Avg Bid
    6 bids

    I need urgent work requires Verilog expertise. It also includes a short report. More details on chat.

    $83 (Avg Bid)
    $83 Avg Bid
    20 bids

    I need to design a 4 bit adder in verilog. I will provide more details in the chat.

    $49 (Avg Bid)
    $49 Avg Bid
    6 bids

    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results

    $199 (Avg Bid)
    $199 Avg Bid
    2 bids

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    $122 (Avg Bid)
    $122 Avg Bid
    5 bids
    $40 Avg Bid
    6 bids

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    $249 (Avg Bid)
    $249 Avg Bid
    7 bids

    Need help program FPGA with Artix-7 using Verliog.

    $174 (Avg Bid)
    $174 Avg Bid
    5 bids

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    $243 (Avg Bid)
    $243 Avg Bid
    1 bids

    Implement the Zen Protocol in the FPGA and update the Mining App

    $1696 (Avg Bid)
    $1696 Avg Bid
    3 bids

    questions on Hardware Design Language and Programmable Logic Regarding Verilog or System Verilog questions. - Writing a function / typdef struct /identifing the types of errors, ... - (pulse width modulation, frequency dividers, counters, sorting, generating a sequence like a Fibonacci sequence, finite state machine, test benches, math functions

    $35 (Avg Bid)
    $35 Avg Bid
    6 bids

    Make a serial interface system using Verilog

    $67 (Avg Bid)
    $67 Avg Bid
    4 bids

    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width

    $274 (Avg Bid)
    $274 Avg Bid
    7 bids

    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width

    $204 (Avg Bid)
    $204 Avg Bid
    5 bids

    Design of a signal generator using verilog hdl. Should be done using Vivado Design Suite . More details in chat.

    $38 (Avg Bid)
    $38 Avg Bid
    6 bids

    image watermarking baed on dct algorithm in verilog code, need to implement in xilinx board

    $304 (Avg Bid)
    $304 Avg Bid
    4 bids

    Part 1: Dynamic Patterns Using LEDs Requirement In this part, you are required to write a Verilog code that produces at least four different dynamic patterns, that is changing with time with reasonable speed. And those patterns are controlled by switches. Features • Use the most left switches to change the patterns. • Design your own patterns. • Use

    $190 (Avg Bid)
    $190 Avg Bid
    8 bids

    I have a verilog game. I need a freelancer to change the resolution of the game and add a background.

    $88 (Avg Bid)
    $88 Avg Bid
    2 bids

    Hello, I have developed the full game in verilog, but I need help with a game over screen to pop up with the player loses all of his lives or a win screen with the player has beaten the game. I will provide you with all the code, mifs, rams, and I just need help to implement the win and game over screens.

    $324 (Avg Bid)
    $324 Avg Bid
    3 bids

    I want to implement the Ethernet connection. The deliverables are as follows -Verilog code to run on a Spartan 6 Board - (xc6slx100) -simulation time diagrams (more details will be given to the winner) - The code should be able to transmit and receive data at 1000mbs.

    $685 (Avg Bid)
    $685 Avg Bid
    7 bids

    Simple project, that basically should detail the observed waveforms and max frequency of given code.

    $35 (Avg Bid)
    $35 Avg Bid
    8 bids

    Hi Behailu D., I noticed your profile and would like to offer you my project. We can discuss any details over chat. conversion python to verilog

    $70 (Avg Bid)
    $70 Avg Bid
    1 bids

    I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be

    $242 (Avg Bid)
    $242 Avg Bid
    4 bids

    A calculator has to bee designed using System Verilog. It includes designing ALU, memory and system controller.

    $202 (Avg Bid)
    $202 Avg Bid
    2 bids

    I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made --

    $215 (Avg Bid)
    $215 Avg Bid
    2 bids

    Code needs to be ported from Matlab to Verilog

    $165 (Avg Bid)
    $165 Avg Bid
    5 bids

    Verilog Task with Vivado and Quartus 2. Should be familiar with schematic design in Altera Quartus 2.

    $53 (Avg Bid)
    $53 Avg Bid
    5 bids

    ...with MAX10 10M50DAF484C7G FPGA * ____________ Final Products: ____________ -A software-level block diagram showing the connections between the System Verilog modules described in pdf -System Verilog implementations of the modules described in pdf. -Valid hardware output. Final Note: Please attach any necessary files with a brief description of the

    $42 (Avg Bid)
    $42 Avg Bid
    1 bids

    1) Design a Finite State Machine (FSM) using Verilog to control the taillights of a 1965 Ford Thunderbird. 2) Implement your design on FPGA

    $234 (Avg Bid)
    $234 Avg Bid
    2 bids

    ALU Design as per instructions in Verilog Task . Simulation done using Icarus VERILOG

    $31 (Avg Bid)
    $31 Avg Bid
    11 bids