Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
1. System architecture (design a multi header linescan CCD system that connects to a PC via ethernet. System would be based on microntroller and CPLD/FPGA)
2. Schematic designing
3. PCB layout designing in Altium
4. Firmware development
5. SDK/DLL in C# for interface with windows based software
6. test utility to view data from the controllers . To be made in C#
I have some really old Verilog code that was generated from some obsolete hardware (~30 years old, specialized and no longer made). Unfortunately this recreation took into account numerous hops done for timing... so it's pretty messy. What I would like is for the Verilog code to be cleaned up without altering the gates (so equivalent logic, just removing the confusing hops). Typically you...
I need someone who will teach me verilog from scratch. Online teaching is preferred. I will prefer at least 20 classes.
The classes must include explaining diffenent types of verilog code for ADL stuffs like sequential circuit, memory, combinational circuit with test bench as well. Interested candidates please contact me. Thanks in advance.
Interfacing a high-speed ADC ( with lvds ouput) with Spartan - 6 based FPGA board
I have a TI ADC board ( high speed with LVDS output), I need to acquire data out of the board using an FPGA ( Nexys 3 - Spartan 6 FPGA - board). The data must be acquired out of the ADC board, processed in FPGA and dumped on a PC.
I need a Verilog USART code to work in a Spartan 6 FPGA.
The USART need be:
Start bit + 8 Data Bits + even parity check + 1.5 Stop bits . The 1.5 stop bits is to implement an error detection, you don't need do anything with this just take 9th(parity) and 10.5(error detect) bits as part of the data, the upper function check parity and error, from 10.6 time cud be consider as next byte.
adder register with 2 input (i.e. A, B), Clock, reset
32 bit adder register with 2 input (i.e. A, B), Clock, reset
need to use Qurtus 2 (Altera ) software
Write the Verilog code for a 32-bit Adder with registered inputs and outputs
Write the Testbench code in Verilog and verify your design works as intended using VCS
The inputs are: reset (active low), input1, input2, clock
The output por...
Read all instruction in attached file.
and specially i want full project like option A.
To keep with our the original plan I would like to still keep this as Option A
LAB Marks out of 10 and Project out of 5
The project work will be more involved (see the Project document for details)
On top of this I would like to present two other options:
LAB Marks out of 12 and Project out o...