|Design and implementation of MPEG-2 encoder on Altera FPGA
||Design an MPEG-2 encoder IP Core in Verilog or VHDL to compress a video signal resolution 640x480. The input images will be in the YCrCb color space. The IP core arquitecture should be Pipeline.
||C Programming, Verilog / VHDL, FPGA
||Sep 1, 2015
|Implementation of multi resolution filter bank in fpga
||I want to implement two types of multi resolution filter banks : using coefficient decimation method, and using frequency response masking method ,the implementation should be done using fpga kit (altera),using vhdl code.
||Matlab & Mathematica, Verilog / VHDL
||Aug 30, 2015
||Aug 30, 2015Ends - 6d 10h
|Vlsi architecture for a run-time multi-precision reconfigurable Booth Multiplier
||A reconfigurable multi-precision Radix-4 Booth multiplier structure must be designed. The reconfigurable 8 x 8 bit multiplier unit can be cascaded to form a multiplier that can adapt to variable input precision requirements. The number of bits can be extended by concatenating more stages together. For example, four 8 x8 bit units can be used to build a 16 x 16 bit Booth multiplier. In our proposed...
||Digital Design, FPGA, Testing / QA, Verilog / VHDL
||Aug 30, 2015
||Aug 30, 2015Ends - 6d 2h
|VHDL/FPGA basics to profession
||Practical private full course " simulation" +
debug with VHDL+ using Communication protocols (USB, Ethernet, Wi-Fi etc)
+ full project with full life cycle.
To gain the needed hands on experiance
Using ARM, Xilinx
||Electronics, FPGA, PCB Layout, Verilog / VHDL
||Aug 29, 2015
||Aug 29, 2015Ends - 5d 10h
|Design and implementation of SPI interface
||To write the VHDL code for the behavioral specification of the SPI Slave and Master Interface and to implement the write and read operation on SRAM using CPLD board.
||Verilog / VHDL
||Aug 26, 2015
||Aug 26, 2015Ends - 20h 45m
|need help in Verilog AMS
||I need help in designing using Verilog-AMS
please PM for more details
||Electrical Engineering, Electronics, Matlab & Mathematica, Microcontroller, Verilog / VHDL
||Aug 23, 2015
||Aug 23, 2015Ended