Verilog / VHDL jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    244 jobs found, pricing in AUD

    Hi there Please check the document

    $44 / hr (Avg Bid)
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    6 bids
    FPGA Design 6 days left

    Hi there Please check the document!

    $19548 (Avg Bid)
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    5 bids

    I need to implement floating point single precision algorithm (add,sub,mul,div)(standar IEEE754) on unit DSP48E1. I need a File Register on 48bit, a priority encoder on 32b, an exponent unit where is stock the sign and exponent and a sequencer(Delay Mealy automata) who give the comand to DSP. Can anybody help me? Thank you!

    $334 (Avg Bid)
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    4 bids

    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

    $182 (Avg Bid)
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    15 bids

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    $161 (Avg Bid)
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    4 bids
    200418_Verilog 5 days left
    VERIFIED

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

    $65 - $104
    Sealed
    $65 - $104
    4 bids
    Conceive SDR GnuRadio blocs 4 days left
    VERIFIED

    This project aims at conceiving GNU-Radio blocs for receiving / transmitting modulated radio messages using Software Defined Radio (SDR). I need a software component lib called "gr-beaglesdr" of a software-defined radio receiver and transmitter combined with suitable hardware device BeagleSDR. It can be used to listen to or display data from a variety of radio transmissions and also send...

    $911 (Avg Bid)
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    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

    $40 (Avg Bid)
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    9 bids

    I want a freelancer for making a project who have strong knowledge of mpi and Openmp c++.If any one interested let me know so we can discuss it further Your task is to implement an initial serial version of the program, where it takes an image as an input and then produces an output image after applying the stencil matrix(Laplacian ) on the input image. Then, you should try to optimize the co...

    $193 (Avg Bid)
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    1 bids

    This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.

    $606 (Avg Bid)
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    4 bids

    I have Program pLc program and Hmi design for academics project just to simulating the code with software need basic help

    $26 (Avg Bid)
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    I have IC cards or integrated chip cards that i needed to write on them. So, i am looking for simple SW and support for successful testing of this beta version design. My design and solution is almost the same as access control however it has its own different use cases. So, let’s assume that I need to create SW solution for access control within a hotel or company using IC card i...

    $370 (Avg Bid)
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    4 bids

    translate c++ code in systemc and implement constrained random verification methodology.

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    5 bids
    build a software 3 days left

    translate c++ code in systemc. and implement constrained random varification methodology.

    $56 (Avg Bid)
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    Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code.

    $232 (Avg Bid)
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    8 bids
    build a software 3 days left

    translate a C++ code in systemc module.

    $40 (Avg Bid)
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    3 bids

    you have to translate C++ code in systemc language.

    $43 (Avg Bid)
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    I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir...

    $199 (Avg Bid)
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    SoundLocator 3 days left

    Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position

    $807 (Avg Bid)
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    Serializer & Desrializer Implementation using ZC706 and MTX

    $38 / hr (Avg Bid)
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    6 bids