|FPGA Altera to Xilinx RTL conversion
This project is for conversion of a current RTL from Altera to Xilinx Spartan 6 FPGA.
The deliverables are the complete project source codes on free ISE WebPACK environment and compile instructions.
The project is not involving any hardware deliverables, only the project source codes, so if any hardware is required for this development, in the form of development boards/etc, is assumed ...
||Electronics, Verilog / VHDL, Microcontroller, Electrical Engineering, Embedded Software
||May 29, 2015
|Ripple carry Adder and carry select Adder.
||Need to compile the code in the compiler and bring out the outputs in synopsys tool i.e. the design and Layout diagrams.
||Electronics, Verilog / VHDL, Electrical Engineering
||May 29, 2015
|ns2 routing simulation - open to bidding
||ns2 wireless communication project.. if interested contact me at [The administrator removed this message for encouraging communication outside Freelancer.com, which breaches our Terms and Conditions - Section 13:Communication With Other Users.]
if interested contact me at [The administrator removed this message for encouraging communication outside Freelancer.com, which breaches our Terms and...
||Circuit Design, Electrical Engineering, Electronics, Matlab & Mathematica, Verilog / VHDL
||May 26, 2015
||May 26, 2015Ends - 4d 14h
|VHDL Fixed Point Implementation, PWM IP Core
||Urgent Help in VHDL Programming for:
1) 32-bit Fixed Point PWM IP Core
2) Using WISHBONE interconnect
3) Includes creating Test Benches for simulation and Synthesis for board testing in Xilinx environment.
4) The pwm must take in a fixed point pwm input (52.35% duty cycle) and output a pwm accordingly.
Job is urgent, good money offered. Detailed specs attached.
||FPGA, Verilog / VHDL
||May 25, 2015
||May 25, 2015Ends - 3d 9h
|Design Digital clock using VHDL
I want a vhdl code for a digital clock to present hours and minutes in board
of spartan 3 . The code should be wrriten by the freelancer him/her self not from copy from internet.
A report should be included .
||Engineering, Verilog / VHDL, Electrical Engineering
||May 24, 2015
||May 24, 2015Ends - 2d 21h