Despite being away from his family, Vietnam local Van Loi Le continues to support his loved ones back home. How? Through Freelancer!
1. Can You make your own version of hardware decoder based on the decoding algorithm. the number of bits however should be remain the same is 64×64,(the decoding methods SISO decoding and Chase Pandiah, type 2 Chase algorithm) and after simulate the decoder on Xilinx ISE and coding in VHDL. 2. and write a brief report explanation how is the hardware structure work and etc.
I need coding VERILOG code for BMI calculation that can be run in Quartus software and burn in ALTERA DE2 board. maximum 80usd
BId only if u can do only the second Part for $50 and within 3 days stereoscopic vision system the aim stereo vision uses two adjacent cameras to creat a 3d image of the world . A depth map can be created by comparing the offset of the corresponding pixels from the two [login to view URL] for real time stereo vision the image data needs to be processed at a reasonabale frame rate .real-time stere...
in this project i need just read a analog signal on altera cyclone 5 board and also to realize pt1 element with simple response a(t)=(1-e^-t/T)....it's a simple project and i can explain you in more detail ....so i just want this to signal at the out i.e on gpio pins
We are looking for one freelancer to develop FPGA software for Cryptonight mining using Xilinx Virtex UltraScale+ FPGA VCU1525 card. You will have to program an FPGA card that I will provide, to work for crypto mining. Is necessary also customize mining software that works under Windows to by able to works with the FPGA. Software must have to be perfectly optimized. You will work in our office...
- PCI transmition logic implement with ZC102 board and Xilinx PCI Solution v1.3 - windows device - sample wndows program
Build a radio communication system which can transmit and receive voice signals over ISM band. Design the system with LabView and USRP NI 2901. You can choose the parameters such as modulation techniques as you like.
I want someone to make a 40 minutes video to teach me how to Use cadence tool to synthesize digital circuit from Verilog code and simulation and do the static timing analysis and static power analysis in a given digital circuit which contains XORs and Multiplexers
A very simple oscilloscope developed using Verilog on Altera software, this project will be based on DE1-SoC Board and is expected to be concluded within a week. Only experienced FPGA engineers please.
I am having difficulties in finishing my final year project. I would like to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not...
Serializer & Desrializer Implementation using ZC706 and MTX
I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo get servos' position by using fou...
Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's
I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir...
Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position
I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [login to view URL] Please respond directly with any questions such as specific mining software and such.
I need to create and minimize 2 small VHDL entities and their corresponding architectures. Can anyone help? I will provide with some files that are the basics to this, but still need to create 2 more. You need to be expert in VHDL language and have knowledge of computer architecture.
I am looking for someone who is familiar with and have access to the following Electronic systems/subjects: - Op-Amps - Multisim - FPGA/Quartus PRime - Mbed Microcontrollers - Digital Analogue converters (DAC) - using R-2R Ladder If you do not have relevant skills and access please do not apply Thank you
Is it possible to make an custom made Arduino Pro Mini PCB? It needed to be made trough easyeda pcb and components from 1206 package Remove all holes traces that are x out. Remove reset button ? It needed to be programmable by and FTDI1232 programmer as regular arduino pro It also needed to added some other components to the board.I have a template that needed to be edited on easyeda, that y...
I have some work in MATLAB i need this work to be finished asap (1-2 days lower bids would be preferred i have more work like this so i want serious freelancers Time wasters are not allowed to bid here NOTE: Milestone will be after seeing the full work
I am looking for a freelancer to help me with my project. The skill required is Verilog. Project is to write verilog code for digital alarm clock an will be simulating in Modelsim and will need testbenches as well. message me for more details
I am looking for a person who will make FPGA NIST5 Cryptocurrency miner. I need full unrolled NIST5 core. NIST5: blake512 -> groest512 -> jh512 -> keccak512 -> skein512 Perfect performance: 1x (Example: FPGA at 400MHz clock generates 400Mega Hash / secound) Language: VHDL FPGA: Xilinx 7 series
Hi This is my research project. i want to design a video codec h.264 processor for face recognition. i this project i wrote verilog hdl coding and completed Ai algorithm for face recognition. so the next steps is to do the cross compilation of h.264 verilog coding with AI Algorithm. so iam expecting that to complete cross compilisation of h.264 verilog code with Ai algorith...
projekt może być oparty na chipie ADV7181
Hi, I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption. - Encryption data output size can vary from 16-bit to 512 bits. - Prime number generation: two random prime number generated through LFSR and should be stored in FIFO - For every iteration different public and private key pairs should be produced. Kindly cont...
We are working on nexys video board and we are trying to access DDR3 memory using IPCORE in vivado design suite software. We want to read and write data into DDR3 memory using nexys video board.