Verilog

Dear sir I have more than 9 years experience in digital design using verilog please message me

Hello! Please check my reviews to know a bit about me. It would be great if I could help you out. Thank you! :)

Hi, I am a post graduate power electronics engineer and having very good experience in product design and development. I am excellent in embedded programming using pic, dspic controllers and MATLAB codding for Power projects, Boot loaders, EEprom. I designed sine wave inverters for standalone and grid tie Inverters. I designed projects like Off line UPS up to 3 KVA, synchronous rectifiers, Solar MPPT chargers, Battery chargers ,Grid tie inverters design with PLL and feedback control circuit emergency light of 66W and Online UPS control cards, Battery Charging power supplies, LED drivers for PWM controlling and dimming, SMPS, Power supplies. I have experience in schematics and PCB design experience in Altium and ORCAD. I am ready to work for you. Please contact for further discussion.

Hello, I have a good experience in designing RTL using Verilog/SystemVerilog as well as writing a testbench to test the RTL code I will provide you all of your requirements as you mentioned Please tell me more details about your project so that I can research and help you to do that. Hope we will have a chance to work together! Regards, Binh

Hi very good morning...! i am professor in engineering college, teaching and working on verilog. kindly brief about your project .Let chat and share more info. Waiting for your response thanks

I work at Broadcom Limited doing custom memory verification, synthesis and design. If you want a TCAM, SRAM, OTP, or MRAM design I'm your guy. Since I do not have access to my work's tools, I'll be using Icarus Verilog for simulation, Xilinx ISE for the synthesis (or the tool that you provide), and I'll also get you formal verification coverage using a symbolic simulator (ACL2).

Has a good knowledge of verilog, 3 year professional experience. Done of couple of projects in bachelors and masters as well.

I am an Senior Engineer who works at high tech company for three years, i have been working on FPGA based capital market product which is already in a stock exchange. i have good knowledge in advance verilog designs as well as software designs for hybrid systems. i am pretty sure i can do this project with good quality. Also note that i am an expert in automated testbenches specially in systemverilog tbs, also i have designed overall fully automated UVM tb for exchange product. i hope you will give me this project since i am the best person for this job. Also please note that if you want this project tb in UVM then will take longer amount of time. Also i am following best verlilog coding practices to achieve good timing less combination logic registered interface. Also will definitely achieve > 90% code coverage since i am using system verilog based Tbs (Can inject random transactions).

Hi, I can secure your memory using AES encryption with ECB mode. I already have verified AES ECB hardware cores and tested with Xilinx flatform. Throughput can be configured from 1 Gbps to 12 Gbps with 100 MHz clock. Can provide best sources utilization for your throughput requirement. I can provide you 1. Synthesizable RTL code for AES ECB mode (already completed) 2. C model for test vector generation (already completed) 3. Verification with C model. and automatic script for questa-sim (already completed) 4. Synthesis script for synopsys design compiler 5. Code Coverage Report (90% coverage already meeting) 6. Detailed drawings of FSM, block diagrams and verification diagrams used in project. This is my second project in freelancer. Since i'm new to freelancer, Please feel free to discuss about project budget. I only concerning a good review and a reasonable budget from this project. Best Regards, Aruna