hello friend, as per your requirement. i have experience in verilog as i am a design engineer. I know all about verilog FSM,test bench and its verification. As you said the project is not big then i can do it easily within time line. I do many ptojects in verilog like i2c master, slave, controller, sPI Controller, Interface of sdram, spi,onchip memories,ethernet,uart,jtag and many more. i use modelsim for verification environment. so allow me to do your job.