ASIC CHIP DESIGN

Closed Posted May 17, 2015 Paid on delivery
Closed Paid on delivery

Hi,

I need ASIC designer to make ASIC chips design.

Will PM with you the details.

Electrical Engineering FPGA Software Architecture Verilog / VHDL

Project ID: #7689147

About the project

16 proposals Remote project Active Jun 23, 2015

16 freelancers are bidding on average $710 for this job

ahmedmohamed85

Dear sir I have more than 8 years experience in digital design using FPGA and ASIC please check my profile also please message me so that we can discuss

$526 USD in 10 days
(507 Reviews)
8.1
zarnescugeorge

Hello! I know there are a lot of good freelancers out there! But I really have the experience you need! I worked 5 years in ASIC design at Heitec, Infineon and Microchip companies! If you need my help I am here! More

$250 USD in 14 days
(95 Reviews)
7.4
uetian09ee506

I am an Electrical Engineer having specialization in Electronics and Control, working as Lab Engineer at FAST National University Pakistan, at Electrical Department. Now a days i am also doing my MS degree in Electrica More

$555 USD in 7 days
(255 Reviews)
7.3
loi09dt1

A proposal has not yet been provided

$555 USD in 10 days
(155 Reviews)
6.7
SANGITAR

i have proficiency in electronic and digital circuit design,VHDL,FPGA, i am ready to take on the task,you can expect 100 percent accurate answers.

$2631 USD in 10 days
(5 Reviews)
4.2
crobert114

Hello, We are three guys doing Ph.D. in VLSI design in Canada. We are working in digital and mixed signal design. We are very familiar with FPGA, VHDL, Cadence. Please let me know your project details. Thanks.

$555 USD in 10 days
(2 Reviews)
0.0
manikandanvlsi13

Hi, I'm a full fledged ASIC designer. Working under Both Synopsys & Cadence ASIC flow from RTL-to-GDS at 45nm, 32nm, 28nm. Moreover I personally having those two ASIC flow software in hand upto 2020 license , if you ne More

$680 USD in 5 days
(0 Reviews)
0.0
Elecguru011

HI, I have experience in FPGA as ASIC design , converting VHDL / Verilog to IC Layout using Magic . See my profile . Regards , Ahme

$500 USD in 10 days
(1 Review)
0.0
rrl123

hello I more than 12y of experience in ASIC-fpga with Cadence, modelsim or Synopsys. RTL with verilog or systemverilog Tape out done at AMS 0.35um and TSMC 90nm and 65 nm Can you explain me in more details what do More

$722 USD in 3 days
(0 Reviews)
0.0
hainam311

A proposal has not yet been provided

$333 USD in 10 days
(0 Reviews)
0.0
atulvlsi

Hi, We are group of VLSI design engineer with good industry experience. Could you please provide more information about the project.

$777 USD in 15 days
(0 Reviews)
0.0
cbsinghece

A proposal has not yet been provided

$888 USD in 30 days
(0 Reviews)
0.0
Barabarabara

A proposal has not yet been provided

$444 USD in 10 days
(0 Reviews)
0.0
Ariffsh

Design Success story begins from plan, anticipate the issue much prior to the implementation. i had been through these process several times and perfected to execute and handle design to GDS. Efficient debugging skills More

$722 USD in 10 days
(0 Reviews)
0.0
dvigurus

Hi, Thanks for your time for reading our personal message. We are experienced working in different protocols such as USB/SATA/PCIe/UART/SPI/I2C and AHB/AXI/APB, also in developing the verification environment usi More

$555 USD in 15 days
(0 Reviews)
1.0
jaganmp

A proposal has not yet been provided

$666 USD in 9 days
(0 Reviews)
0.0