CMOS-VLSI on Virtuoso Cadence -- 2

In Progress Posted 6 years ago Paid on delivery
In Progress Paid on delivery

c Integrated Circuit (ASIC) implementation of an N x

N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through

MOSIS.

CAD/CAM Electrical Engineering

Project ID: #15744950

About the project

1 proposal Remote project Active 6 years ago

1 freelancer is bidding on average $231 for this job

rubelsarkar161

Hi, I do have cadence virtuoso. I can provide you layout design of your project if you have schematic. If you want layout can be provided in 130/180 nm TSMC node LVS,DRC will be cleaned Thanks...

$231 USD in 200 days
(5 Reviews)
4.1