(BIST) Built in self test verilog/ vhdlcode for memory
₹12500-37500 INR
Paid on delivery
The aim of the project is to design a BIST controller to insert and detect the faults (defect) like Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim.
Need Simulation waveforms for the same.
Project ID: #17806030
About the project
1 freelancer is bidding on average ₹30000 for this job
Hi, I hope you are doing well and enjoying digital design. I believe implementing a design right form modeling until verifying it on an FPGA is always a very special experience. Throughout my 3+ years of experie More
