ASIC IP RTL/TB Development - Looking for Engineers -- 3

Job Description :-

We are a group building high performance configurable ASIC IPs that can fit inside a variety of products ranging from low power IoT ASICs to good performance Desktop/Server ASICs. The work centers around some of the advanced areas of chip design such as Cache Coherency, Virtual Channels and traffic performances, Pipelining for high-speed data and control logic, Clock-gating and Power-gating etc.

The work is in an advanced prototype stage and we plan to launch a product down the line. The team has people with chip-design experience in MNCs over decade and background of colleges as Indian Institute of Technology.

Job Requirements :-

1) We are looking for freshers or junior engineers who can code RTL and sub-unit Testbench from scratch with engineering supervision and broad level Microachitecture and Architecture Specs.

2) The person needs to have an excellent/good Verilog/SystemVerilog/Perl [login to view URL] coding will be Perl mixed Verilog/SV.

3) Knowledge of Make, Python, Bash is an advantage, but not mandatory.

4) The person needs to have a good understanding of the basic building blocks of an ASIC/FPGA design. Understanding of advanced concepts (as coherency) is an advantage, but not mandatory.

5) The person should have good energy to finish work in a timely manner, passion for RTL/TB coding, attention to details and humility to learn from right feedback.

Who can Apply :-

1) Fresher/junior engineers looking for an opportunity.

2) People looking for training/upscaling in the domain can apply.

3) People looking to explore in-depth from scratch ASIC design can also apply.

Benefits :-

1) Opportunity to work in complex ASIC product design from scratch.

2) Opportunity to learn alongside experienced and passionate engineers.

3) Monthly Stipend/Remuneration.

4) Facility to work remotely.

How To Apply :-

Please apply answering below points -

1) Your expertise level in Perl, Verilog, System Verilog - Beginner/Intermediate/Expert.

2) Which area between design/verification you are more interested in.

Placeholder budget/timeline. Details to be discussed.

If you are sending a proposal, please be available in chat so that details can be discussed.

Skills: Perl, Verilog / VHDL, Very-large-scale integration (VLSI), FPGA Coding, Digital ASIC Coding

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About the Employer:
( 0 reviews ) Kolkata, India

Project ID: #30526350

10 freelancers are bidding on average $531 for this job


Dear sir, I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL programming. Also, I am experienced with Vivado, ISE, Vivado IPs, SDK, Quartus, Design Compiler, IC Compiler and othe More

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Hello I have extensively worked on FPGAs and Embedded Systems. Have taped-out an IC in 130nm. Worked extensively on both VHDL and Verilog. I am currently Co-Founder of a firm in Pakistan. My company is functional sinc More

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$500 USD in 7 days
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Hello, My name is Ewan McNeil and I am a recent college graduate in Computer engineering in Montreal Quebec, this posting was very interesting to me and I would put my self in the junior engineer looking for an opportu More

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Hi , I'm interested in this project I am expertise in verilog intermediate system verilog and beginner in perl scripting ,I'm interested in more verificationn field

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Hi, I am design Verification engineer having 10+ years of experience. Good expertise in verilog SV UVM perl etc languages. dm for more details

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Hi, I Have 2+ years experience in Verilog and System Verilog, I worked on different Tools Xilinx,Vivado, Questasim, Cadence....I hope i will definitely help to your project. [login to view URL] expertise level in Verilog, System V More

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Hi, I have 10+ exp in Verilog & VHDL coding and RTL designing & I can ensure that I can complete it on time. My expertise levels: Perl -> Begineer Verilog/SV -> Intermediate Interest -> Design Please More

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