do verilog multiplier uses a shift and add algorithm. The multiplier uses 2 phase clocking system

The inputs for the multiplier are A (A3, A2, A1, A0) and B (B3, B2, B1, B0), Reset and Start.

The outputs for the multiplier are O (O7, O6, O5, O4, O3, O2, O1, O0), and Finish

The operation of the multiplier is as follows

1. When Reset = 1 the system is reset

2. When start = 1 the following occurs

a. Load A on the first 1

b. Load B on the first 1

c. After n cycles the output is stored in O and the Finish output is asserted

d. There is no change to the output after subsequent cycles.

In this phase you are to describe the HDL code that you will use and the specify the names and timing types

(s1, s2, etc) for all signals used to implement the system

Prepare a well organized and well written report that describes your analysis, model development, and simulation results.

Skills: PHP, Software Architecture

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