Hello , how are you? Hope all is fine !
Regarding your project I have long experience with FPGA and VHDL . I work with both intel and Xilinx FPGAs , SoC and SOPC.I use Quartus II and Vivado IDEs accordingly. I test timing compliance through timing analysis . I deliver tested , neat and well-commented code that can be reused or modified for future development.
Regarding the Video CODEC part , I have worked before on H.264 standard and I implemented soft decoder (C++ code just for testing as part of R&D) and I managed to implement the blocks (having understood the algorithm with the aid of third-party tools) as VHDL code. I can show how how far I have gone .
More to be discussed once you contact me .
BR,
M.T.