Help with UVM test bench
I need a UVM test bench example for a synopsis VIP.
VIP has connection to DUT and is driving all the [url removed, login to view] also have a top level Sequencer:_sysVirtualSeqr to do this. My goal is to create two agents that will generate the PIO packet and driver it to top level sequencer.
The bench will have 2 Agents.
* will have sequencer connected to Agent-2
* will have sequences to create PIO write and PiO read with (address and data).
*sequence should get the above address and data
*sequencer should drive it to the VIP's sequencer. (Eg: [url removed, login to view](_env._sysVirtualSeqr.root_virt_seqr.driver_transaction_seqr);)
VIP will not return a ack. So to keep bench happy
* For PIO_wr ack should be returned immediately.
For PIO_rd wait for data back and then send ack
Please create such a system verilog UVM bench ? I need it pretty quick. Once i have this I can discuss more on this.
Note: The agent sequences should generate sequences using uvm_create(req), start_item(req) and sequencer with get_next_item.
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My passion enables me to do this job for more details message me, we can negotiate about the project and its nature of work. Relevant Skills and Experience / Proposed Milestones $55 USD - .