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VhdlVerilogEng

@VhdlVerilogEng

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$20 USD / Hour

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Canada (6:45 AM)

Joined on July 27, 2010

$20 USD / Hour

3 years of Silicon Valley experienced EE engineer with IC chip designing experience. Expert in VHDL, Verilog, Cadence, Synopsys tools. FPGA design and firmware programming experience. C/C++, Java and assembley language experience.

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