FPG CPLD serial stream decoder.

Dear sir, I am ready to discuss the budget with you if you have a problem with it, I have more than 7 years experience in digital design using FPGA,I have read the attachments carfully, and i can do it perfectly, I can make this design for you using CPLD or FPGA, waiting your reply, Best Regards;

Hello! I can deliver the code for you in 5 working days. To demonstrate the functionality of the code I will provide ModelSim simulations for you. Regards, Botond

Hello! I can do your project right away! For only 100 dollars net! Your project is interesting but a quite hard! I assure you that with my experience I can solve your project immediately! Please contact me and send me your detailed requirements! Have a nice day! Hello! If you have digital design projects I can help you right away! I have 8 years experience in designing digital logic circuits using VHDL and implementing them in FPGA. I was a digital design engineer at Grenoble Institute of Technology! Right now I am a teaching assistant at an important university in Europe. I teach the digital logic design and VHDL modules laboratories! Have a nice day!

Hello, I could do this task if you had clear Functional Specifications. Can you explain what the H1/2/3 are for? ... read your description, try to understand and you'll catch that some points are missing. Thanks, Ashot

Hi there, I can write for you in vhdl code. I guess you want it as a simulation. But if you like I have evaluation board of ALTERA and XILINX I have 12 years experience with FPGA's and PLD's. Thanks, Amir

I have been working for various local and international companies on a variety of projects and have recently shifted to online work. The last client that I worked for was a US based client working on smart grids I worked on Cyclone IV FPGA. I have a very good reputation with the client. This is briefly what I did in my last job assignment: Altera Cyclone IV based System Design and Development: Board bring-up, Test codes & Application Firmware & debugging of application firmware written by other developers. Designed and implemented architecture for comprehensively testing all peripherals connected on a Smart Grid System Board. Also implemented various parts of application firmware [RMII, MDIO, Ethernet, EMIF, SerDes, CRC, UART] I can show you my work if you like [over skype screen sharing etc.] Your project seems quite straight forward. I should be able to show you a working simulation within a week and a working design in another week. Best Regards Syed Farhan

I am new to using the freelance bidding system. However I have over 25 years in the electrical engineering field. I have 10+ years experience as a digital ASIC designer. I have also developed for Altera's line of FPGA's. I have designed many serial interfaces for fully released ASIC designs for Analog Devices Inc. I am very familiar with Manchester encoded data streams and clock extraction. This project should be very straight-forward. I include the two week time frame to allow myself sufficient time due to my inexperience with the freelance approach to design. I am being cautious. I am fairly confident of finishing sooner. Thank you for your interest.

Hello There I am working as Associate Verification Engineer at a local semiconductor company. I know verilog, system verilog and Normally I develop testbenches in system verilog using UVM as methodology. I think I can do this job within 7-10 days. I use IUS for simulation and other purposes. I am available 4 hours each day. You can knock me Thanks & Regards

Hi, I can do this project. I have some experience to write the VHDL or Verilog code for FPGA devices.

I, Keyur Mahant working in One of the leading University of India as Asst. Professor in Electronics and Communication Engg. And Space Technology Center as Project Scientist in which, I am working on “Single Event Upset Characterization of FPGA”. In addition I had a one year experience to work with Physical Research Laboratory (PRL), Ahmadabad. In PRL I was working on Chandrayan-2 payload design where I had developed a DAQ for X- Ray florescence for elemental analysis