FPGA ALTERA - VHDL project

Dear sir I have more than 10 years experience in embedded systems design using fpga, I have DE2 board and the same camera, please message me so that we can discuss best regards

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

Hi, I hope you are doing well and enjoying digital design. I believe implementing a design right form modeling until verifying it on an FPGA is always a very special experience. Regarding your project, I had built fully-verified tens of RTL projects and implemented them on Spartan 6. Throughout my 3+ years of experience in the field, I had the joy of designing and implementing a part of LTE's physical layer right from the Matlab model, through RTL coding, simulations, and back-end stages. I also built many other designs such as a MIPS processor design, Can satellite that composed I2C, UART, and many FIFOs to handle data. All my designs were verified successfully on either Xilinx's Spartan S6, S3, or Altera's Cyclone V FPGA. I would love to hear your thoughts and requirements for the delivery soon. Have a good night :))

Hello Sir/Ma’am It’s a privilege to know that you are going through my proposal. However, I would like if you can spend a little more time and check my portfolio as well. That’s how you can see what I can do for you as well as the quality I offer. I have read your project description and I am confident that i can do this. I am 100% sure that I can meet your expectation. Also, I will priotize deadline and review work for as much as possible if need be. I will be more than happy if you can please consider me for this work of yours and I will try my best so as not to disappoint you Thanks FPGA, Image Processing, Verilog / VHDL

Hi, I recently completed my Ph.D. at Johns Hopkins University in Electrical and Computer Engineering last year where I worked on visual processing systems (efficient systems inspired by the brain mechanisms). My work involved advanced modeling in MATLAB for proof of concept and then transitioning to implementation on FPGA using VHDL for real-time, low-power operation. I then even implemented the design in VLSI technology (ASICs). Overall, I have advanced MATLAB and VHDL experience for image processing and will definitely be able to help you with this project with quality and in a timely manner. Thank you, J. Molin

An interesting task. I am ready to help you out on this project. Please contact me if you are interested to give the work to me..

Greetings, My name is Ayam Ajmera and I am a recent graduate of information and communication technology (ICT) from Ahmedabad University. Recently I was a technical intern at Indian Space Research Organisation (ISRO), Ahmedabad. There, I was responsible for RTL module development for Chandrayaan-2 Lander using VHDL. I worked on space grade Virtex 4 during the course of this project. I was working on the team which built a system to perform soft-landing on the Lunar surface. The gist of this project was to find craters and boulders on lunar surface and avoid landing a rover on those places which are full of hazards (here hazard being craters and boulders that can topple the rover). During the course of this project, we wrote a working matlab as well as C code for this functionality and then we implemented this project on VHDL using the C and matlab codes as reference. We wrote these codes without using any inbuilt functions, so that it was easy to implement it using VHDL. The project you are proposing has some similarities with the project I've done. If you need to ask me something, you can contact me on this app or you can mail me at ajmeraayam@gmail dot com. Waiting for your response. Thanks, Ayam Ajmera

Look me up on internet.

Versatile knowledge in both vhdl & verilog. Having 10+ years of industrial experience. Relevant Skills and Experience Versatile knowledge in both vhdl & verilog. Having 10+ years of industrial experience